1. Field of the Invention
The present invention relates to a technique for implementing a semiconductor integrated circuit device such as a magnetic random access memory (MRAM) which has, as a single memory cell, an element structure for storing “1” or “0” information by using a magneto-resistive effect, integrates and arranges the memory cells in a matrix, and adds control circuits such as a decoder circuit and sense circuit to the peripheral portion of the memory cells so as to allow a read operation or a write operation by random-access to an arbitrary bit and, more particularly, to an MRAM which has a current peak suppressing circuit which suppresses a current peak generated immediately after the start of the write operation.
2. Description of the Related Art
An MRAM is a device which performs a memory operation by storing “1” or “0” information by using a magneto-resistive effect. MRAMs are expected as one of candidates of universal memory devices capable of realizing nonvolatility, high integration, high reliability, low power consumption, and high-speed operation and are being developed by various manufacturers.
There are two well-known magneto-resistive effects: GMR (Giant Magneto-Resistive) and TMR (Tunneling Magneto-Resistive) effects. The GMR effect uses a phenomenon in which the resistance of a conductive member sandwiched between two ferromagnetic layers changes depending on the direction of spin in the upper and lower ferromagnetic layers. However, the MR ratio that indicates the ratio of a change in magneto-resistance value is as low as about 10%. For this reason, a read signal of stored information is small. The most difficult point for implementation of an MRAM is how to ensure the read margin. An MRAM of this type is therefore presently regarded as impractical.
As a typical element that exhibits a TMR effect, an MTJ (Magnetic Tunnel Junction) element is known. An MTJ element has a multilayered structure including an insulating film sandwiched between two ferromagnetic layers made of a metal and utilizes a change in magneto-resistance due to a spin polarization tunneling effect. More specifically, when the spin directions of the two, upper and lower magnetic layers of an MTJ element are parallel, the tunnel probability between the two magnetic layers through the tunnel insulating film is maximized. As a result, the resistance value is minimized. On the other hand, when the spin directions are anti-parallel, the tunnel probability is minimized. Accordingly, the resistance value is maximized. To realize the two spin states, one of the two magnetic films normally has a fixed magnetization direction and is set not to be influenced by external magnetization. This layer is generally called a pinning layer. The magnetization direction of the other magnetic film can be programmed by the direction of an applied magnetic field to be parallel or anti-parallel to that of the pinning layer. This layer is generally called a free layer. The free layer stores information. There are currently some MTJ elements which have a resistance change ratio, i.e., an MR ratio of 50% or more. They are becoming the mainstream of MRAM development.
In writing data in an MRAM using MTJ elements, to reverse the magnetization direction of the free layer, a current having a predetermined value or more is supplied to bit and word lines which pass through the respective memory cells while running perpendicularly to each other. The magnetization direction of the free layer is controlled by the magnitude of the generated synthetic magnetic field.
In a read, a voltage is applied between the two magnetic films of an MTJ element corresponding to a selected bit, and the resistance value is read from the current flowing through the MTJ element. Alternatively, a constant current is supplied to a selected MTJ element, and a voltage generated between the two magnetic layers is read out.
An example of an MRAM using such an MTJ element is reported in, e.g., “A 10 ns Read and Write Non-Volatile Memory Array using a Magnetic Tunnel Junction and FET Switch in each Cell”, ISSCC 2000 Digest of Technical Paper, p. 128 (paper 1). In addition, a detailed example of the arrangement of the write circuit in the MRAM is reported in, e.g., “MRAM-Writing Circuitry to Compensate for Thermal-Variation of Magnetization-Reversal Current”, 2002 Symposium on VLSI Circuits Digest of Technical Papers, p. 156 (paper 2).
FIG. 1 shows the detailed example of the arrangement of the write circuit described in paper 2. The technique disclosed in paper 2 is based on a constant current write method. In this technique, a plurality of selector circuits are connected to one constant current source and selectively operated in accordance with an address input, thereby selectively supplying a current to a cell to be write-accessed.
In this method, however, a current source output line represented by a node A or B has a relatively large parasitic capacitance. It mainly contains the parasitic capacitance of the output line from the current source and the diffusion capacitance of the plurality of selector circuit portions. Additionally, as shown in FIG. 1, the PMOS transistor serving as the current source is normally ON. In the standby state, the node A or B is therefore charged to the power supply voltage (Vcc) as the source potential of the PMOS transistor. If the MRAM is activated in this state, and a write operation request is issued, a current is supplied to a specific write line in accordance with an externally input address. The current source controls to prevent any current more than necessary from flowing to the selected memory cell. However, a current having a predetermined value or more flows due to the charged current from the relatively large parasitic capacitance. Especially, a large current peak is generated immediately after the start of the write operation. When a stable state is obtained, the effect of current control by the current source appears. However, if the current peak immediately after the start of the write operation is large, a write error occurs in all cells connected to the write line. This problem is predicted to become more conspicuous as the number of repetition of selector circuits increases or the parasitic capacitance of the output line from the current source increases in accordance with the increase in chip size.
As described above, in the conventional semiconductor integrated circuit device, a large current peak is generated immediately after the start of the write operation. This decreases the write operation margin and lowers the reliability.